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Last login30-11-2018
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English interpretation
MB board. Mother Board / Main Board
NB Notebook Note Book, North Brige Northbridge.
CPU Central Processing, Central Processing Unit. Divided into two brand AMD, INTEL.
PCI Peripheral Component Interconnect standard Peripheral Component InterConnect
DDR, DRAM, DIMM, MEMORY memory, the memory has experienced SDR, DDR, DDR2, DDR3
HDD hard disk interface points IDE, SATA, SAS, SCSI, solid state media separation, magnetic disk.
CDROM drive, the interface points IDE, SATA. Functional sub-ordinary CD-ROM, DVD drive, burner
FDD, Floppy Floppy Drive, has been eliminated, replaced by U disk and removable hard disk
IDE Hard disk / CD-ROM, an interface
MCH Intel motherboard Northbridge
GMCH built-in integrated graphics Intel Northbridge
ICH Intel motherboard Southbridge chip
LAN card, LAN also has the meaning of the corresponding WAN represents extranet or WAN.
AUDIO AC97 CODE card
Analog VGA monitor connector
DVI Digital Display Interface
HDMI high-definition interface, digital video / audio interface
PIO, LPT printer port, parallel port.
SIO, COM port
SPI, FLASH, FWH BIOS, Basic Input Output System. Integrated in the motherboard CMOS. BIOS software, CMOS hardware, do not confuse the two.
MOUSE, M / S mouse or mouse interface flag
KEYBOARD, K / B keyboard or keyboard interface flag
Front FRONT, front panel
Rear REAR, rear
FAN fan
IR infrared
SPDIF Sony & Philips Digital Audio Interface is divided into coaxial and fiber-optic interfaces
SPEAKER speakers, speakers
BIOS WP BIOS write protection, the purpose is to prohibit flashing BIOS.
WOL WAKE #, WOR RI # Wake on LAN, ring wake.
USB Universal Serial Bus, Universal Serial Bus
DDR Double Data Rate Double Data Rate
SATA Serial Advanced Technology Attachment Serial Advanced Technology Attachment
VCC, VDD power supply
GND, VSS Ground
5VSB 5V standby voltage, ATX power purple line, 220V plug outputs. SB = Stand By auxiliary power supply circuit
3VSB 3VSB Southbridge internal ACPI controller or PCI devices to provide power, 3.3V, converted from the 5VSB.
VBAT battery voltage is 3V power diode after the name. Equivalent RTCVCC, VCCRTC, 3V_BAT
VCC3 VCC VCC12 3.3V 5V 12V voltage supply.
VCORE CPU_VDD CPU core power supply.
VTT bus termination voltage, the role is to stabilize the signal on the bus.
VTT_CPU VTT_GMCH VTT_FSB FSB_VTT VCCP front-side bus-powered, front-end notebook is powered bus, 1.05V, desktop CPU power supply is about 1.2V
VTT_DDR memory bus power supply, memory, the main power supply 1/2
Bus-powered VLDT HT1.2V AMD platform, 1.2V
VCC_VID desktop 478 CPU VID circuit in the work required voltage, 1.2V, without this voltage, CPU can not issue a combination of VID
A 2.5V power supply VDDA AMD's CPU needs, the lack of CPU power this will not work, and may lead to no CPU power.
5VDUAL / 3VDUAL 5V / 3V dual switching power supply, standby power supply time from 5VSB / 3VSB, by VCC5 / VCC3 after power supply
BOOT BST bootstrap end, the purpose is to enhance the driving signal voltage on the tube
FSB Front Side Bus FSB connection Intel CPU and North Bridge, the new board was renamed QPI
DMI, HUBLINK connection intel Northbridge and Southbridge bus
LPC I / O bus connections and Southbridge
CLK clock signal, CLOCK Abbreviation
RST # reset signal, RESET # Abbreviation
PG, POK, PWRGD, PWROK Power Good, good signal power, without the # indicates active high with # indicates active low.
EN EN turn signal, ENABLE Abbreviation, # indicates a high level without open, and SHDN # equal.
SHDN # SHUTDOWN Abbreviation, with # represents low closed, open high level, and EN equal.
RTCRST # Real Time Clock RESET #, real-time clock is reset, leading to the South Bridge, this signal is low will clear CMOS. It is to remove the BIOS settings and restore the factory to factory defaults.
RSMRST # Resume Well Reset is used to reset the controller ACPI, sleep Southbridge reset logic. RSMRST # signal can also be understood as a standby voltage notification Southbridge good signal, or some chipset called PWRGD_SB AUXOK. Notebook: Reset ACPI Sleep logic controller settings, but also that a good signal S5 Southbridge standby status IBM has ACPI register
SLP_S3 # Southbridge issued is high exit S3 standby state, S3 sleep, S4 hibernation, S5 off low.
SLP_S4 # Southbridge issued is high exit S4 sleep state and enters the S3 or S0 state.
SLP_S5 # Southbridge issued is high, quit S5 off into the S4 / S3 / S0 state.
PSON # ATX power connector on the green line, the low level when the power is turned on and start working.
PWRBTN # Power Button power switch, S5 off, PWRBTN # low to wake the system, enter S5 for 4 seconds to force a shutdown state.
PWRSW # Power Swich, usually the front panel switches.
VID0 to VID5 6 voltage identification pin, high-low combination, consisting of a set of binary code.
VTTPWRGD VIDPWRGD description FSB power supply is normal, usually sent to CPU, VRM, clock.
After VRMPWRGD Power Manager normally generated VCORE, Southbridge sent to a power good signal, tell Southbridge VCORE voltage is normal
ATXPWROK ATX power gray lines, power good. After conversion circuit Northbridge and Southbridge sent to complete the automatic reset.
PLTRST # INTEL Southbridge reset signal of the platform, a low level is reset, normal operation is 3.3V
A_RST # AMD platform chipset Southbridge issued reset. During normal operation of 3.3V
PCIRST # PCI Reset, low level is reset. PCI reset signal is 3.3V during normal operation
CPURST # CPU reset signal, INTEL chipset Northbridge sent to CPU, AMD chipset Southbridge distributed CPU, normal operation is high
APU_RST # AMD chipset APU is sent to a reset signal is reset on a dummy load.
CPUPWRGD CPU voltage is normal, INTEL Southbridge chipset is usually sent to CPU, NV, SIS chipset Northbridge to the CPU
LDT_PG AMD chipset South Bridge sent a signal to the CPU is on the PG dummy load
APU_PG AMD chipset South sent a PG signal APU, is the dummy load on PG
IDERST # IDE reset signal is 5V during normal operation
SUSB # SUSC # INTEL equivalent of SLP_S3 #, SLP_S4 #
ADDRESS address lines, abbreviated A
DATA data line, abbreviated D
Common point is also the name of Quanta; VIN supply input
Regulators in VOUT, VOUT is the output voltage; PWM in, VOUT is the voltage sense input
VCNTL operating voltage, the control voltage
VREF reference voltage, the reference voltage
HSTNC line synchronization
VSYNC vertical sync
SMBCLK / SMBDATA System Management Bus System Management Bus clock / data
SPI Swrial Peripheral Interface Serial Peripheral Interface
FB feedback
DRV drive
PHASE Phase
ISEN current detection I Sense
VSEN voltage detection V Sense
OCSET Over Current Set Overcurrent setting
CPUVDD_EN NVIDIA chipset Southbridge issue turned off the CPU power supply enable signal
HTVDD_EN NVIDIA chipset Open HT bus powered, 1.2V
After MEM_VLD Nvidia chipset, SLP_S5 # control the generation of memory power, memory power supply PG signal is returned to the bridge
CPU_VLD Nvidia chipset CPU power supply normal PG signal, and VRMPWRGD Intel platform as
HT_VLD Nvidia chipset, HT bus-powered normal PG signal, and VTTPWRGD Intel platform as
SUS Suspend, Suspend shorthand
Quanta Quanta
Compal Compal
Wistron Wistron
Inventec British industry
Mitac Mio
Clevo sky
Fic public
Msi MSI
Asus Asus
Ecs Elite
Topstar Topstar
DELL Dell
SONY Sony
toshiba Toshiba
Adapter detection signal received ACPRESENT Southbridge, Southbridge part of the lack of this signal will not boot
Customizable GPIO pin, the program needs
BL / C # Quanta machines, battery mode low battery indication. Battery mode, a high level indicates that the battery voltage is low, normal low. Under Adapter mode meaningless
D / C # high discharge DIS, CHG low charge
ACOFF shutdown signal adapter, the battery discharges. Generally when the program control of the battery calibration accuracy, EC to set high. Similar signals also ADOFF, D / C #, DISCHARGE
BIOS_CS # CE # EC signals to select the BIOS chip. A high level is not selected, select LOW
BIOS_OE # BIOS received CS # to issue an export permit. Allowed high, low allows
BIOS_WE # brush BIOS allows low potential
SPI_MISO MI input, O outputs, SPI bus Features: Point to Point
LPC_FRAME LPC bus frame cycle signal
4 address data signal LPC AD0-AD3 LPC bus
LDO3 LDO5 linear 3V 5V power supply
ILIM Current limit threshold setting
Oscillating Frequency Set TON PWM chip
BATLOW # indicates low battery power is low, electricity is one of the conditions on laptop Southbridge
Touch pad touchpad
MUTE # mute switch
PACIN, ACIN, ACDET adapter into the detection threshold voltage to check the data sheet
-EXTPWR, EXTPWR #, ACPRN, ACOK, ACAV_IN adapter detection output. Some high, some low, look at the chip manual
PS_ID DELL adapter identification, middle needle
LIMIT_SIGNAL HP middle pin adapter generally above 6V
DCIN charging main power chip
CC_SET charging current to the charging chip set
ICTL CHLIM SRSET battery charge current setting
CLS ACLIM machine using current and the charging current distribution set, adapter current to prevent overload
VCTL VADJ battery charging voltage settings
CELL-SET battery core number, serial number
ICM adapter output current detection after
VL REG LDO linear voltage
Under VDDP tube drive signal supply
FSTCHG BAT_CRG IBM open battery charge
HWPG Quanta machine, each phase voltage signal generated by PG
THERM temperature detection, thermistor and resistor divider is detected
TEMP_MBAT battery temperature detection signal
MOS tube temperature detector THRM chip power management chip, when the thermistor and resistor divider is lower than the value of his
VRHOT VR_TT # power management chip overtemperature indication
STPCLK # Southbridge clock signal to the CPU is stopped, C2 state of ACPI
STPCPU # Southbridge issued to clock down the CPU clock, ACPI C3-state
DPRSLPVR Southbridge issue, deep sleep open signal, high into the C4 state of ACPI
PM_PSI # CPU distributed power management chip energy-saving signal to reduce a phase power supply, N-1
VCC_TXLVDS Northbridge inside the set was powered with LVDS
POWER JACK adapter interface
MBATV M_BATVOLT S_BATVOLT main battery cell sampling signal S M sub battery
BATMON_EN IBM in the open cell voltage detection circuit signal
DOCKING Notebook Docking Station Dock connecter below
MBDATA MBCLK battery management bus EC management
LID_EC # closing lid switch sleep switch, not low
DNBSWON # Quanta machine, EC sent a high level of signal power switch triggered Southbridge
LCD_BLON display backlight is turned on
C_LINK Southbridge and Northbridge bus. MT remote management technology
Finger Print fingerprint scanning
Camera Webcam Laptop Camera
DIBP DIBN modem bus
New Card Socket new card expansion card interface
Card Reader card readers, control a variety of readers. 1394
G-Sensor accelerometer to detect
TPM security chip
CLK_PCIE_3GPLL Northbridge clock 100M
DREFCLK Northbridge set was VGA module 96M differential clock
DREF_SSCLK Northbridge set was LVDS clock module
FRAME # frame cycle, this signal is normal, on behalf of AD data transfer cycle start and end
LFRAME # LPC bus frame period,
SKIP # power chip mode selection
PRO # overvoltage and undervoltage protection switch, closed high, low, open
OVP overvoltage protection
UVP OCP undervoltage protection, overcurrent
ON3 ON5 3V, 5VPWM on signal
Tube drive signals DH UGATE HDRV
Under DL LGATE LDRV tube drive signal
LX PHASE phase detection
COMP Compensation (Compensatory abbreviation word), to eliminate its internal error. Excellence.
TIME voltage swing rate. Setting voltage rise slope
ICH INTVRMEN high level to turn on the VRM modules Southbridge, electricity is one of the conditions on INTEL Southbridge
NBSWON # Quanta machine, laptop power button signal
BKLTCTL notebook backlight adjustment, DPST_PWM
BKLTEN notebook backlight is turned on, LVDS_BLON
DISP_ON lamp voltage Open notebook
HWPGD_VDR video memory PWGD
HWPG_GFX set was PWGD
CLKRUN PCI clock run
MCP NV Bridge
SENSE detection
DISCRETE_ENABLE open all channels of discrete graphics
VTT_VDDIO_PG AMD platform memory bus load powered PG
CHG_EN Charge Enable
ACPRES test adapter
CE # CS # chip select chip select. Superiors sent to the lower signal. And almost frame period
OE # RD # output enable, output enable
WE # WR # writing brush allows
H_GTREF CPU_GTLREF CPU reference voltage, two-thirds of the 3 bus-powered, no voltage can cause not run code
TH_DET IBM in thermistor detection pin voltage below 0.5V
WIRELESS_ON / OFF # wireless switch panel
HT_SHUT # temperature control signal
CAS # column selection signal
RAS # signal line option
IRDY # DEVSEL #: device select signal
THERMDA CPU thermal diode cathode
THERMDC CPU thermal diode anode
Signals the down OVERT # temperature reaches a certain value
ALERT # warning signal
HW_PROTECT # HW temperature, followed by the hardware protection
OTP_RESET # overtemperature protection circuit will jump, does not protect the temperature is normal
THRMTRIP # CPU and other chip overtemperature sent Southbridge, this signal is valid, Southbridge will be forced into off state S5
Wireless Wireless
Transformer bridges, transformers
RJ45 Ethernet port
RJ11 telephone line interface
RS-644 LVDS Interface
KBCRSM KBC keyboard, RSM wake
Design Current design current
Low High Low and High
Signal emitted by the normal bridge SEQ_SW
LRESET # LPC bus reset signal
VCTRL adjustment
ADAPTER Adapter
CCV output voltage and the specified voltage error amplifier output, the main role of offset voltage
CCI specified output voltage and current error amplifier output, the main role of compensation current
MGNT management
INTRUDER # chassis intrusion detection, general pull-high
ERROR Error Error
ACK response
BUSY Busy
VCCSUS3_3, V5REFSUS Southbridge standby 3V, 5V power supply
VCC3_3 V5REF Southbridge 3V, 5V power supply
V_CPU_IO CPU FSB 1.2V
SOFT-STAR SS Soft-start, referring to the slow rise Ratings
SCL Serial Clock
SDA Serial Data
MDC MODEM cat, modem
Analog analog signal
Digital digital signal
FORCE_OFF # Asus machine forced shutdown signal, active low
TMDS DVI signal cable
HPD hot plug signal, said high insertion
DAC converter module
R / L R for the right channel, L is the left channel
INT_MIC built-in microphone
DOCK_MIC external microphone
AMPL, AMPR amplifier left and right channels, AMP is the amplifier
SENSE_A SENSE_B card chip headset insertion detection
Head Phone out HP out headphone output
RBIAS # bias resistors, current chip set
Bias voltage VBIAS
USBRBIAS USB bias resistor
PCMCIA Personal Computer Memory Card International Association
NTC negative thermal sensitive resistance lower temperature, the higher the resistance
PTC thermistor being warmed higher the temperature, the higher the resistance
Short straight, short
VREG5 VREG3 chip linear voltage TPS
ENTRIP TPS chip PWM open
V5FILT TPS chip linear power supply
APIC Advanced Programmable Interrupt Controller Southbridge This module requires a reference clock 14M
BREQ0 # 0 bus request
DBI # data bus inversion in high and low I / O
DIVN0-3 # dynamic bus inversion signal and 64 data signals are driven together, sending I / O signals are inverted
DP # parity data I / O
IGNNE # ICH to the CPU ignores the value is incorrect, I normally low
SMM system management mode
SMI # ICH system management interrupt to the CPU enters SMM management I
NMI non-maskable interrupt
PGD_IN ISL62xx power management chip to receive PGD_IN before issuing CLK_EN #
VDIFF VW FB COMP ISL62XX set by connecting the resistor capacitor compensation module
VO / ISEN CSP / CSN sense the output current
FS RT TON TONSEL FSET FSEL oscillation frequency setting. Through a resistor to ground to set oscillation frequency. Triangular wave generated by an internal OSC
VCCSENSE VSSSENSE voltage detection and voltage detection circuit
VSEN RTN CPU seat detection signal, power management chip connected to the positive and negative CPU
FSB frequency FSLA FSLC FSLB clock chip set to determine CPU clock frequency
MODE Mode
VCC3SW IBM in the 3.3V linear output
TB VREGIN20 IBM Power chips in
CPOUT VCPIN TB chip bootstrap circuit, VCPIN back after the boost voltage
SWPWRG IBM chip standby reset
DISCHARGE IBM battery discharge. Generally when the program control of the battery calibration accuracy, EC to set high.
PWRSHUTDOWN # IBM chip detection of TB over-temperature and over-voltage will cause this signal low
SRC PDL PDS MAX8725 is used to control the power switch driving with battery-powered switch, provided the source by the SRC, adapter status
PKPRES # MAX8725 can detect if the battery indicates low battery
TS1 # BAT_PRES # battery detection signal when it detects the battery is low
Source Source
IV @ EV @ SP @ integrated graphics discrete graphics display module
VCC_POR # exceeds the set value voltage chip automatic reset, reset EC notebook
AUX auxiliary power supply, AUX is generally used to enable LAN and other auxiliary power supply
NV_OVERT # NV graphics overtemperature
Cacitive Sense SW pointing
Digital Light NUM_LED #
CAP_LED # uppercase Lights
TP_CLK TP_DAT touchpad signal
BL_DA LCD_BL_PWM backlight adjustment
FAN0_TACH fan, TACH detection
PD # P # signal means closed meaning, with # to work high.
SYS_PWROK whole system voltage I3 I5 good including CPU, DRAM memory issue after PG equivalent VRMPWRGD, normal
PROCPWRGD PROC = Processor power processor partial good. I series CPU is the heart of the power generation is good; II / III non-core CPU power is good, CPU after receiving the signal emitted SVID
MEPWROK AMT power-good, equivalent CLPWROK
DIS PM GM UMA DIS / PM significant independence, UMA / GM was set
ALWON 3 / 5V standby power supply is turned
= PP3V3_FET PP Apple's power, represented by a MOS FET with the back switch mode converter tube voltage, the voltage is typically converted to standby after boot
SYS_ONEWIRE, ESD green apple adapter interface management lines, ESD anti-static Acronym
ALWAYS has always existed, and always mean
IHDA bridge sound modules
INVERTER transformer
BEEP buzzer
SERIAL I / F COM port module, the signal has RXD TXD RSR RTS CTS DTR Rl DCD
PARALLEL I / F module parallel port, there are signals INIT # SLCTIN PD SLCT Pe Busy Ack Error Alf Strobe
HDSTBN-4 # HDSTBP-4 # I / O host differential data strobe signal, this signal is used to synchronize the multiplexed 64-bit data signal and the signal DIVN
FSB ADS # signal, address strobe, this signal has been filtered words * * denotes a CPU to work
BRO # CPU bus request signals for
BNR # Under a request, I / O (input and output)
LOCK # signal master lock, FSB signal, all the CPU cycles are subject HLOK # ADS # signal and the control signal. When HLOCK # signal sent by the CPU, GMCH memory interface can not use I / O
BPRI # bus priority requests I input
DEFER # signal indicates that this transaction could not ensure the orderly completion, O
DRDY # data is ready, waiting for data I / O
DBSY # data bus is busy, bus use is low, not high I / O
RESET # Reset / Reset, all the internal data is invalid
RS # 0-2 in response to the controller asserts that the current processing status of the transaction I
TRDY # is ready from the device can accept data I / O
HIT # unchanged cache request bus I / O
HITM # cache request bus kept changing, and you assume the task of providing the bus I / O
ADSTB # 0-1 I / O lock A32 # and REQ # 0-4 in their up and down along the corresponding responsible ADSTB0 # REQ # 0-4 and A # 3-16, ADSTB1 # A # 17-31 responsible
REQ # command requests I / O
DPWR # I Northbridge control signal is sent to the CPU, reducing data input voltage processor cache, the cache turned off when not activated when the data line data.
DSTBP # 0-3 I data clock signal in a period of four this will be driven, in DSTBP and DSTBN falling released. DINV # signal indicates that the polarity of the data I / O
DSTBN # 0-3 data signals in one clock cycle will be driven four this in DSTBP and DSTBN falling released. DINV # signal indicates that the polarity of the data I / O
HA # 0-31 I / O host address bus, 32 HA address signals and address bus connected to the CPU, pay attention to the CPU address bus is negated
HD # 0-63 I / O host data bus, 64-bit data with the CPU data bus, the data signal transmission on the processor is set to Anti
DPRI # limited the right to request the bus.
DINV0-3 Data Bus Inversion, data bus inversion indicates polarity 64-bit data, the source-synchronous signal, the input / output signals
A20M # 20 address bits masked signal to the CPU Southbridge
DPRSTP # Southbridge issue, Deep Sleep stop signal to stop the high level of C4 ACPI sleep state to stop
DPSLP # issued by the South Bridge to the cpu and mch, usually the processor from sleep to deep sleep state, the input signal
FERR # CPU floating point error made, there can not be masked, CPU drive to ICH, Low, O
System management interrupt SMI # I I
STPSLK # stop the clock, Southbridge to the CPU clock is stopped, enter the power saving mode I
CPU initialization signal INIT # ICH issued, L1 cache floating point I
INTR can be shielded interrupt, ICH interrupt signal to the CPU, the first bus cycle and then off I processing
PWRGOOD power OK, Southbridge sent to CPU, CPU does not work without this signal I
PROCHOT # CPU overtemperature indication, notice Southbridge I / O when the temperature reaches the set temperature
Issue this signal power indication signal, sleep and deep sleep PSI # processor can improve the efficiency of the load.
BSEL total election choice for selecting the desired CPU frequency I / O
A [31: 3] # This group defines a 32-bit physical address space, the maximum memory address space to 4GB. These address signals ADSTB [1: 0] # rising or falling is sent to the buffer.
BCLK [1: 0] FSB clock, the two different BCLK signal, determines the frequency of the bus, the input signal;
BPM [2: 0] #, BPM [3] Breakpoint Monitor for detecting the status of breakpoints and cpu performance for input / output signals;
D [63: 0] # data signals in one clock cycle will be driven four times in DSTBP [3: 0] # and DSTBN [3: 0] # falling edge to be released. Each 16-bit data signal and a pair of DSTBP and DSTBN signal corresponds. DINV # signal indicates that the polarity of the data.
A signal DBR # Data Bus Reset, not the processor, is the driving DEBUG port started working, when the system has this port, this pin is kept empty pin, the output signal
IERR # Internal Error, is a result of the processor has an internal error, usually accompanied by a shutdown signal or by an external processor core logic into question, the output signal
ITP_CLK [1: 0] is not a signal processor, is a copy of the BCLK signal, do not exist only in DEBUG ports on your system, the input signal
LINT [1: 0] Local APIC Interrupt, and INTR signal is compatible, are asynchronous signals can be set through the BIOS, the input signal
PRDY # Probe Ready signal processor debugging tools show debug ready signal, the output signal
PREQ # Probe Ready probe request signal. This signal is requested by the processor debug tool debug operation, the input signal
The sleep signal SLP #
TDI Test Data In, transmitting a series of test data to the processor, the input signal
Reset signal TRST # Test Reset of test
CPU_STOP_L CPU to stop working, Active Low.
H_STOP_L Southbridge to the Northbridge bus run signal.
DIMM_STR_EN memory power-on signal
VDDA_EN CPU 2.5V voltage on signal
DCBATOUT Wistron common point
AD + Wistron adapter from the machine is turned on to generate a voltage, for generating a common point all the way, another way to isolate the battery
ACAV_IN charging adapter detection output chip
Standby voltage control signal turns Southbridge part of PWR_S5_EN for Wistron
AD_IN # adapter to the EC of the detection signal, active low
KBC_PWR_BTN # Wistron generated by pressing the switch trigger signal to the EC
LID_CLOSE # closing lid switch
After CLK_EN # CPU power supply is normal, given the low level can be used to start the clock
High temperature G792_RST # microarray emitted when the temperature is normal
After CK_PWRGD Southbridge receive VRMPWRGD, given the high level, the clock for opening
GPU graphics processor, graphics core
AGP Accelerated Graphics Port for older cards
PCI-E interface to each external device fast, new graphics card, so the use of the card
ODD drive
Lithium battery voltage BATT +
+ 5VALW 5V Always voltage is 5V standby voltage, under general adapter mode automatically generated, PWM power supply
+ 5VA 5V standby voltage, and it is the same 5VALW
+ 5VAL 5V standby voltage, L represents a linear, LDO
+ 3VO 3.3V voltage output, O = OUT
CLOCK Clock
ADP_PRES adapter detection, active high
APWROK HM6X above chip AMT power-good
After receiving RSMRST # SUSCLK Southbridge sent 32K clock
SRTCRST # ICH9 later added a RTC reset signal name is SRTCRST #
Southbridge RTC's power VCCRTC INTEL
RTC voltage VDDBT_RTC_G AMD chipset, AMD's battery is dead will cause no reset point does not shine, such as failure
3.3V standby voltage VDDIO_33_S AMD single bridge
1.1V standby voltage VDDCR_11_S AMD single bridge
SLP_M # INTEL ICH8 chip set from the beginning to support AMT feature with this model AMT power control, most machines do not use.
DRAMPWROK INTEL chipset memory power good, PCH sent to the CPU
LAN_RST # INTEL chipset South Bridge internal NIC module reset. After the normal power supply card, motherboard controller card issued to bridge the reset signal, can be understood as the card power-good signal. If the board does not use the integrated NIC INTEL, and this signal is forced to ground.
SLP_LAN # LAN subsystem sleep control, power control card. If you do not use INTEL motherboard integrated NIC, this signal is not used. INTEL such as the use of integrated network card that supports Wake on LAN, then the signal will go high standby, does not support the Wake on LAN, this signal follows SLP_M # or SLP_S3 #.
Overtemperature indication output THERMTRIP CPU's
A series of second-generation power VCCSA needed three generations of CPU. Full Name System Agent (memory controller, DMI, PCIe controllers, and display engine) power supply is short to the memory controller, DMI power display power connector, PCIE controller, voltage range from 0.65V to 1.05V, can modify the voltage values ??of VID pin foot VCCSA
AC_PRESENT bridge receives a detection signal adapter
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Post time 17-7-2015 21:42:33
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Discover card
Post time 10-6-2016 17:23:15
Post time 20-11-2018 11:01:20
